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rev. 1.0 5/12 copyright ? 2012 by silicon laboratories SI512/13 SI512/513 d ual f requency c rystal o scillator (xo) 100 kh z to 250 mh z features applications description the SI512/513 dual frequency xo utilizes silicon laboratories' advanced pll technology to provide any frequency from 100 khz to 250 mhz. unlike a traditional xo where a different crystal is required for each output frequency, the SI512/513 uses one fixed crystal and silicon labs? proprietary any- frequency synthesizer to generate any frequency across this range. this ic- based approach allows the crystal resonator to provide enhanced reliability, improved mechanical robustness, and excellent stability. in addition, this solution provides superior supply nois e rejection, simplifying low jitter clock generation in noisy environments. the SI512/513 is factory-configurable for a wide variety of user specifications, including frequency, supply voltage, output format, output enable polarity, and stability. specific configurations are factory-programmed at time of shipment, eliminating long lead times and non-recurring engineering charges associated with custom frequency oscillators. functional block diagram ? supports any frequency from 100 khz to 250 mhz ? two selectable output frequencies ? low-jitter operation ? 2 to 4 week lead times ? total stability includes 10-year aging ? comprehensive production test coverage includes crystal esr and dld ? on-chip ldo regulator for power supply noise filtering ? 3.3, 2.5, or 1.8 v operation ? differential (lvpecl, lvds, hcsl) or cmos output options ? optional integrated 1:2 cmos fanout buffer ? runt suppression on oe and power on ? industry standard 5x7 and 3.2x5 mm packages ? pb-free, rohs compliant ? ?40 to 85 o c operation ? sonet/sdh/otn ? gigabit ethernet ? fibre channel/sas/sata ? pci express ? broadcast video ? switches/routers ? te l e c o m ? fpga/asic clock generation v dd any-frequency 0.1 to 250 mhz dspll ? synthesis fixed frequency oscillator clk+ clk? oe gnd power supply filtering fs ordering information: see page 13. pin assignments: see page 12. si5602 1 2 3 6 5 4 gnd oe v dd clk+ clk? fs 1 2 3 6 5 4 gnd fs v dd clk+ clk? oe SI512 lvds/lvpecl/hcsl/cmos dual xo SI512 cmos dual xo si513 lvds/lvpecl/hcsl/cmos dual xo 1 2 3 6 5 4 gnd oe v dd clk nc fs si513 cmos dual xo 1 2 3 6 5 4 gnd fs v dd clk nc oe
SI512/513 2 rev. 1.0
SI512/513 rev. 1.0 3 t able of c ontents section page 1. electrical specificat ions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 2. pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.1. dual cmos buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3. ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 4. package outline diagram, 5 x 7 mm, 6-pi n . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5. pcb land pattern: 5 x 7 mm, 6- pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 6. package outline diagram: 3. 2 x 5.0 mm, 6-pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 7. pcb land pattern: 3.2 x 5.0 mm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 8. top marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 8.1. SI512/513 top marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 8.2. top marking explanation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 document change list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 contact information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
SI512/513 4 rev. 1.0 1. electrical specifications table 1. operating specifications v dd = 1.8 v 5%, 2.5 or 3.3 v 10%, t a = ?40 to +85 o c parameter symbol test condition min typ max units supply voltage v dd 3.3 v option 2.97 3.3 3.63 v 2.5 v option 2.25 2.5 2.75 v 1.8 v option 1.71 1.8 1.89 v supply current i dd cmos, 100 mhz, single-ended ?2126 ma lvds (output enabled) ?1923ma lvpecl (output enabled) ?3943ma hcsl (output enabled) ?4144ma tristate (output disabled) ??18ma fs, oe "1" setting v ih see note 0.80 x v dd ??v fs, oe "0" setting v il see note ? ? 0.20 x v dd v fs, oe internal pull- up/pull-down resistor * r i ?45?k ? operating temperature t a ?40 ? 85 o c note: active high and active low polarity oe options available. ac tive high uses internal pull-up. active low uses internal pull- down. see ordering information on page 12.
SI512/513 rev. 1.0 5 table 2. output clock frequency characteristics v dd = 1.8 v 5%, 2.5 or 3.3 v 10%, t a = ?40 to +85 o c parameter symbol test condition min typ max units nominal frequency f o cmos, dual cmos 0.1 ? 212.5 mhz f o lvds/lvpecl/hcsl 0.1 ? 250 mhz total stability* frequency stability grade c ?30 +30 ppm frequency stability grade b ?50 +50 ppm frequency stability grade a ?100 +100 ppm temperature stability frequen cy stability grade c ?20 +20 ppm frequency stability grade b ?25 +25 ppm frequency stability grade a ?50 +50 ppm startup time t su minimum v dd to output frequency (f o ) within specification ??10ms disable time t d f o ?? 10 mhz ? ? 5 s f o < 10 mhz ? ? 40 s enable time t e f o ?? 10 mhz ? ? 20 s f o < 10 mhz ? ? 60 s settling time after fs change t frq ??10ms *note: total stability includes initial accuracy, operating temperature, supply voltage change, load change, shock and vibration (not under operatio n), and 10 years aging at 40 c.
SI512/513 6 rev. 1.0 table 3. output clock levels and symmetry v dd = 1.8 v 5%, 2.5 or 3.3 v 10%, t a = ?40 to +85 o c parameter symbol test condition min typ max units cmos output logic high v oh 0.85 x v dd ??v cmos output logic low v ol ? ? 0.15 x v dd v cmos output logic high drive i oh 3.3 v ?8 ? ? ma 2.5 v ?6 ? ? ma 1.8 v ?4 ? ? ma cmos output logic low drive i ol 3.3 v 8 ? ? ma 2.5 v 6 ? ? ma 1.8 v 4 ? ? ma cmos output rise/fall time (20 to 80% v dd ) t r /t f 0.1 to 125 mhz, c l = 15 pf ?0.81.2ns 0.1 to 212.5 mhz, c l = no load ?0.60.9ns lvpecl/hcsl output rise/fall time (20 to 80% v dd ) t r /t f ??565ps lvds output rise/fall time (20 to 80% v dd ) t r /t f ??800ps lvpecl output common mode v oc 50 ? to v dd ? 2 v, single-ended ?v dd ? 1.4 v ?v lvpecl output swing v o 50 ? to v dd ? 2 v, single-ended 0.55 0.8 0.90 v ppse lvds output common mode v oc 100 ? line-line, v dd = 3.3/2.5 v 1.13 1.23 1.33 v 100 ? line-line, v dd = 1.8 v 0.83 0.92 1.00 v lvds output swing v o single-ended, 100 ? differential termination 0.25 0.35 0.45 v ppse hcsl output common mode v oc 50 ?? to ground 0.35 0.38 0.42 v hcsl output swing v o single-ended 0.58 0.73 0.85 v ppse duty cycle dc all output formats 48 50 52 %
SI512/513 rev. 1.0 7 table 4. output clock jitter and phase noise (lvpecl) v dd = 2.5 or 3.3 v 10%, t a = ?40 to +85 o c; output format = lvpecl parameter symbol test condition min typ max units period jitter (rms) jprms 10k samples 1 ??1.3ps period jitter (pk-pk) jppkpk 10k samples 1 ??11ps phase jitter (rms) j 1.875 mhz to 20 mhz integration bandwidth 2 (brickwall) ?0.310.5 ps 12 khz to 20 mhz integration band- width (brickwall) 2 ?0.81.0ps phase noise, 156.25 mhz n 100 hz ? ?86 ? dbc/hz 1 khz ? ?109 ? dbc/hz 10 khz ? ?116 ? dbc/hz 100 khz ? ?123 ? dbc/hz 1 mhz ? ?136 ? dbc/hz additive rms jitter due to external power supply noise 3 jpsr 10 khz sinusoidal noise ? 3.0 ? ps 100 khz sinusoidal noise ? 3.5 ? ps 500 khz sinusoidal noise ? 3.5 ? ps 1 mhz sinusoidal noise ? 3.5 ? ps spurious spr lvpecl ou tput, 156.25 mhz, offset > 10 khz ??75?dbc notes: 1. applies to output frequencies: 74.17582, 74.25, 75, 77.76, 100, 106.25, 125, 148.35165, 148. 5, 150, 155.52, 156.25, 212.5, 250 mhz. 2. applies to output frequencies: 100, 106.25, 125, 148. 35165, 148.5, 150, 155.52, 156.25, 212.5 and 250 mhz. 3. 156.25 mhz. increase in jitter on output clock d ue to sinewave noise added to vdd (2.5/3.3 v = 100 mvpp).
SI512/513 8 rev. 1.0 table 5. output clock jitter and phase noise (lvds) v dd = 1.8 v 5%, 2.5 or 3.3 v 10%, t a = ?40 to +85 o c; output format = lvds parameter symbol test condition min typ max unit period jitter (rms) jprms 10k samples 1 ??2.1ps period jitter (pk-pk) jppkpk 10k samples 1 ??18ps phase jitter (rms) j 1.875 mhz to 20 mhz integration bandwidth 2 (brickwall) ?0.250.55ps 12 khz to 20 mhz integration bandwidth 2 (brickwall) ?0.81.0ps phase noise, 156.25 mhz n100hz ??86?dbc/hz 1 khz ? ?109 ? dbc/hz 10 khz ? ?116 ? dbc/hz 100 khz ? ?123 ? dbc/hz 1 mhz ? ?136 ? dbc/hz spurious spr lvpecl output , 156.25 mhz, offset>10 khz ??75?dbc notes: 1. applies to output frequencies: 74.17 582, 74.25, 75, 77.76, 100, 106.25, 125, 148.35165, 148.5, 150, 155.52, 156.25, 212.5, 250 mhz. 2. applies to output frequencies: 100 , 106.25, 125, 148.35165, 148.5, 150, 155.52, 156.25, 212.5 and 250 mhz.
SI512/513 rev. 1.0 9 table 6. output clock jitter and phase noise (hcsl) v dd = 1.8 v 5%, 2.5 or 3.3 v 10%, t a = ?40 to +85 o c; output format = hcsl parameter symbol test co ndition min typ max unit period jitter (rms) jprms 10k samples * ??1.2ps period jitter (pk-pk) jppkpk 10k samples * ??11ps phase jitter (rms) j 1.875 mhz to 20 mhz integration bandwidth * (brickwall) ?0.250.30ps 12 khz to 20 mhz integration band- width * (brickwall) ?0.81.0ps phase noise, 156.25 mhz n100hz ??90?dbc/hz 1khz ? ?112 ? dbc/hz 10 khz ? ?120 ? dbc/hz 100 khz ? ?127 ? dbc/hz 1 mhz ? ?140 ? dbc/hz spurious spr lvpecl ou tput, 156.25 mhz, offset>10 khz ??75?dbc *note: applies to an output frequency of 100 mhz. table 7. output clock jitter and phase noise (cmos, dual cmos) v dd = 1.8 v 5%, 2.5 or 3.3 v 10%, t a = ?40 to +85 o c; output format = cmos, dual cmos parameter symbol test co ndition min typ max unit phase jitter (rms) j 1.875 mhz to 20 mhz integration bandwidth 2 (brickwall) ?0.250.35ps 12 khz to 20 mhz integration bandwidth 2 (brickwall) ?0.81.0ps phase noise, 156.25 mhz n100hz ??86?dbc/hz 1 khz ? ?108 ? dbc/hz 10 khz ? ?115 ? dbc/hz 100 khz ? ?123 ? dbc/hz 1 mhz ? ?136 ? dbc/hz spurious spr lvpecl ou tput, 156.25 mhz, offset>10 khz ??75?dbc notes: 1. applies to output frequencies: 74.17 582, 74.25, 75, 77.76, 100, 106.25, 125, 148.35165, 148.5, 150, 155.52, 156.25, 212.5 mhz. 2. applies to output frequencies: 100, 106.25, 1 25, 148.35165, 148.5, 150, 15 5.52, 156.25, 212.5 mhz.
SI512/513 10 rev. 1.0 table 8. environmental compliance and package information parameter conditions/test method mechanical shock mil-std-883, method 2002 mechanical vibration mil-std-883, method 2007 solderability mil-std-883, method 2003 gross and fine leak mil-std-883, method 1014 resistance to solder heat mil-std-883, method 2036 moisture sensitivity level msl 1 contact pads gold over nickel table 9. thermal characteristics parameter symbol test condition value units thermal resistance junction to ambient ? ja still air 110 c/w table 10. absolute maximum ratings 1 parameter symbol rating units maximum operating temperature t amax 85 o c storage temperature t s ?55 to +125 o c supply voltage v dd ?0.5 to +3.8 v input voltage (any input pin) v i ?0.5 to v dd + 0.3 v esd sensitivity (hbm, per jesd22-a114) hbm 2 kv soldering temperature (pb-free profile) 2 t peak 260 o c soldering temperature time at t peak (pb-free profile) 2 t p 20?40 sec notes: 1. stresses beyond those listed in this table may cause pe rmanent damage to the device. functional operation or specification compliance is not impli ed at these conditions. exposure to ma ximum rating conditions for extended periods may affect device reliability. 2. the device is compliant with jedec j-std-020c.
SI512/513 rev. 1.0 11 2. pin descriptions *note: supports integrated 1:2 cmos buffer. see section 2.1 ?2.1 . dual cmos buffer? and section 3 ?3. ordering information?. table 11. SI512 pin descriptions (cmos, oe pin 2) pin name cmos function 1 fs frequency selected. 0 = first frequency selected. 1 = second frequency selected. 2 oe output enable. internal pull-up for oe active high. pull- down for oe active low. see ordering information. 3 gnd electrical and case ground. 4 clk clock output. 5 nc no connect. make no external connection to this pin. 6 v dd power supply voltage. table 12. si513 pin descriptions (cmos, oe pin 1) pin name cmos function 1 oe output enable. internal pull-up for oe active high. pull- down for oe active low. see ordering information. 2 fs frequency selected. 0 = first frequency selected. 1 = second frequency selected. 3 gnd electrical and case ground. 4 clk clock output. 5 nc no connect. make no external connection to this pin. 6 v dd power supply voltage. table 13. SI512 pin descriptions (oe pin 2) pin name lvpecl/lvds/hcsl/du al cmos function 1 fs frequency selected. 0 = first frequency selected. 1 = second frequency selected. 2 oe output enable. internal pull-up for oe active high. pull- down for oe active low. see ordering information. 3 gnd electrical and case ground. 4 clk+ clock output. 5 clk? complementary clock output. 6 v dd power supply voltage. SI512 cmos SI512 lvds/lvpecl/ hcsl/ dual cmos* si513 lvds/lvpecl/ hcsl/dual cmos* 1 2 3 6 5 4 gnd oe v dd clk+ clk? fs 1 2 3 6 5 4 gnd oe v dd clk nc fs 1 2 3 6 5 4 gnd fs v dd clk+ clk? oe si513 cmos 1 2 3 6 5 4 gnd fs v dd clk nc oe
SI512/513 12 rev. 1.0 2.1. dual cmos buffer dual cmos output format ordering options support either complementary or in-phase output signals. this feature enables replacement of multiple xo s with a single SI512/13 device. figure 1. integrated 1:2 cmos buffer supports complementary or in-phase outputs table 14. si513 pin descriptions (oe pin 1) pin name lvpecl/lvds/hcsl/du al cmos function 1 oe output enable. internal pull-up for oe active high. pull- down for oe active low. see ordering information. 2 fs frequency selected. 0 = first frequency selected. 1 = second frequency selected. 3 gnd electrical and case ground. 4 clk+ clock output. 5 clk? complementary clock output. 6 v dd power supply voltage. ~ ~ complementary outputs in-phase outputs
SI512/513 rev. 1.0 13 3. ordering information the SI512/513 supports a wide vari ety of options including frequenc y, stability, output format, and v dd . specific device configurations are programmed into the SI512/513 at time of shipment. configurations can be specified using the part number conf iguration chart below. silicon labs pr ovides a web browse r-based part number configuration utility to simplif y this process. refer to www.silabs.com/vcxopartnumber to access this tool and for further ordering instructions. the SI512/513 xo series is supplied in industry-standard, rohs compliant, lead-free, 3.2 x 5.0 mm and 5 x 7 mm packages. tape and reel packaging is an ordering option. figure 2. part number convention example part number: 512pca000104bagr: the series prefix, 512, indicates the device is a dual cm os xo with the oe function on pin 2. the output format code p specifies the outputs are dual in-phase cmos with a 2.5 v supply. the frequency stability code c indicates a total stability of 30 ppm. the fre quency select and output enable code a specifies that the two frequencies are listed in ascending order, with the out put frequency f0 (the lower frequency) selected when fs=0, and f1 (the higher frequency) selected when fs = 1. the de vice?s output enable polarity is active high. the six-digit code is 000104. as specif ied by the part number lookup utility at www.silabs.com/vcxopartnumber , f0 is 155.52 mhz (the lower frequency) and f1 is 156.25 mh z (the higher frequency). the package code b refers to the 3.2 x 5 mm footprint with six pins. the last a refers to the product revision, g indicates the temperature range (?40 to +85 o c), and r means the device ships in tape and reel format. note: cmos and dual cmos maximum frequency is 212.5 mhz. si ot tf t oe pi pk s er i es o u t pu tf orma t oe pi n p ac k age 512 cmos oe on pin 2 6-pin 513 cmos oe on pin 1 6-pin 512 lvpecl, lvds, hcsl, dual cmos oe on pin 2 6-pin a = revision: a g = temp range: -40c to 85c r = tape & reel; blank = trays. x x 51x x xxxxxx x 1 st option code: output format vdd output format 513 lvpecl, lvds, hcsl, dual cmos oe on pin 1 6-pin agr x x 51x x xxxxxx x 3 rd o p tion code: vdd output format a 3.3v lvpecl b3.3v lvds c3.3v cmos d 33v hcsl agr p fs function and output enable package option dimensions a 5x7mm d 3 . 3v hcsl e 2.5v lvpecl f2.5v lvds g2.5v cmos h 25v hcsl fs functionality oe polarity a frequencies in ascending order (fs = 0 selects lower frequency) oe active high c oe active low 2 nd option code: frequency stability a 5x7mm b 3.2 x 5 mm h 2 . 5v hcsl j1.8v lvds k1.8v cmos l 1.8v hcsl m 33v dlcmos(i h) 6 - digit frequency designator code b frequencies in descending order (fs = 0 selects higher frequency) oe active high d oe active low frequency stability total temperature a 100ppm 50ppm b50 pp m25 pp m m 3 . 3v d ua l cmos (i n-p h ase ) n 3.3v dual cmos (complementary) p 2.5v dual cmos (in-phase) q 2.5v dual cmos (complementary) r 18v dlcmos(i h) code description xxxxxx this 6-digit code represents a unique combination of two frequencies. frequencies from 100 khz to 250 mhz ( differential ) or 212.5 6 digit frequency designator code pp pp c 30ppm 20ppm r 1 . 8v d ua l cmos (i n-p h ase ) s 1.8v dual cmos (complementary) () mhz (cmos) are supported. for more info: www.silabs.com/vcxopartnumber .
SI512/513 14 rev. 1.0 4. package outline di agram, 5x7mm, 6-pin figure 3 illustrates the package details for the 5 x 7 mm si 512/513. table 15 lists the values for the dimensions shown in the illustration. figure 3. SI512/513 outline diagram table 15. package diagram dimensions (mm) dimension min nom max a1.501.65 1.80 b1.301.40 1.50 c0.500.60 0.70 d5.00 bsc. d1 4.30 4.40 4.50 e2.54 bsc. e7.00 bsc. e1 6.10 6.20 6.30 h0.550.65 0.75 l1.171.27 1.37 l1 0.05 0.10 0.15 p1.80? 2.60 r0.70 ref. aaa 0.15 bbb 0.15 ccc 0.10 ddd 0.10 eee 0.05 notes: 1. all dimensions shown are in millimeters (mm) unless otherwise noted. 2. dimensioning and tolerancing per ansi y14.5m-1994. ?
SI512/513 rev. 1.0 15 5. pcb land pattern: 5 x 7 mm, 6-pin figure 4 illustrates the 5 x 7 mm pcb land pattern for the SI512/513. table 16 lists the values for the dimensions shown in the illustration. figure 4. SI512/513 pcb land pattern table 16. pcb land pattern dimensions (mm) dimension (mm) c1 4.20 e2.54 x1 1.55 y1 1.95 notes: general 1. all dimensions shown are in mil limeters (mm) unless otherwise noted. 2. dimensioning and tolerancing is per the ansi y14.5m-1994 specification. 3. this land pattern design is based on the ipc-7351 guidelines. 4. all dimensions shown are at maximum ma terial condition (mmc). least material condition (lmc) is calculated based on a fabrication allowance of 0.05 mm. solder mask design 5. all metal pads are to be non-solder mask defined (nsmd). clearance between the solder mask and the metal pad is to be 60 m minimum, all the way around the pad. stencil design 6. a stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder paste release. 7. the stencil thickness shou ld be 0.125 mm (5 mils). 8. the ratio of stencil aperture to land pad size should be 1:1. card assembly 9. a no-clean, type-3 solder paste is recommended. 10. the recommended card reflow profile is per the jedec/ipc j-st d-020c specification for small body components.
SI512/513 16 rev. 1.0 6. package outline diag ram: 3.2 x 5.0 mm, 6-pin figure 5 illustrates the package details for the 3.2 x 5.0 m m SI512/513. table 17 lists the values for the dimensions shown in the illustration. figure 5. si510/511 outline diagram table 17. package diagram dimensions (mm) dimension min nom max a1.061.171.28 b0.540.640.74 c0.350.450.55 d 3.20 bsc d1 2.55 2.60 2.65 e 1.27 bsc e 5.00 bsc e1 4.35 4.40 4.45 h0.450.550.65 l0.901.001.10 l1 0.05 0.10 0.15 p1.171.271.37 r0.32 ref aaa 0.15 bbb 0.15 ccc 0.10 ddd 0.10 eee 0.05 notes: 1. all dimensions shown are in milli meters (mm) unless otherwise noted. 2. dimensioning and tolerancing per ansi y14.5m-1994. ?
SI512/513 rev. 1.0 17 7. pcb land pattern: 3.2 x 5.0 mm figure 6 illustrates the 3.2 x 5.0 mm pcb land pattern fo r the SI512/513. table 18 lists the values for the dimensions shown in the illustration. figure 6. SI512/513 recommended pcb land pattern table 18. pcb land pattern dimensions (mm) dimension (mm) c1 2.60 e1.27 x1 0.80 y1 1.70 notes: general 1. all dimensions shown are in mil limeters (mm) unless otherwise noted. 2. dimensioning and tolerancing is per the ansi y14.5m-1994 specification. 3. this land pattern design is based on the ipc-7351 guidelines. 4. all dimensions shown are at maximum ma terial condition (mmc). least material condition (lmc) is calculated based on a fabrication allowance of 0.05 mm. solder mask design 5. all metal pads are to be non-solder mask defined (nsmd). clearance between the solder mask and the metal pad is to be 60 m minimum, all the way around the pad. stencil design 6. a stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder paste release. 7. the stencil thickness shou ld be 0.125 mm (5 mils). 8. the ratio of stencil aperture to land pad size should be 1:1. card assembly 9. a no-clean, type-3 solder paste is recommended. 10. the recommended card reflow profile is per the jedec/ipc j-std-020 specification for small body components. ?
SI512/513 18 rev. 1.0 8. top marking use the part number config uration utility located at: www.silabs.com/vcxopartnumber to cross-reference the mark code to a specific device configuration. 8.1. SI512/513 top marking 8.2. top marking explanation mark method: laser line 1 marking: 2 = SI512 3 = si513 ccccc = mark code 2ccccc line 2 marking: tttttt = assembly manufacturing code tttttt line 3 marking: pin 1 indicator. circle with 0.5 mm diameter; left-justified yy = year. ww = work week. characters correspond to the year and work week of package assembly. yyww 2ccccc ttt t t t yyww
SI512/513 rev. 1.0 19 d ocument c hange l ist revision 0.9 to revision 1.0 ? updated table 1 on page 4. ?? updates to supply current typical and maximum values for cmos, lvds, lvpecl and hcsl. ?? cmos frequency test condition corrected to 100 mhz. ?? updates to oe vih minimum and vil maximum values. ? updated table 2 on page 5. ?? dual cmos nominal frequency maximum added. ?? total stability footnotes clarified for 10 year aging at 40 c. ?? disable time maximum values updated. ?? enable time parameter added. ? updated table 3 on page 6. ?? cmos output rise / fall time typical and maximum values updated. ?? lvpecl/hcsl output rise / fall time maximum value updated. ?? lvpecl output swing maximum value updated. ?? lvds output common mode typical and maximum values updated. ?? hcsl output swing maximum value updated. ?? duty cycle minimum and maxi mum values tightened to 48/52%. ? updated table 4 on page 7. ?? phase jitter test condition and maximum value updated. ?? phase noise typical values updated. ?? additive rms jitter due to external power supply noise typical values updated. ?? footnote 3 updated limi ting the vdd to 2.5/3.3v ? added tables 5, 6, 7 for lvds, hcsl, cmos, and dual cmos operations. ? moved absolute maximum ratings table. ? added note to figure 2 clarifying cmos and dual cmos maximum frequency. ? updated figure 5 outline diagram to correct pinout. ? updated table 17 on page 16. ? updated ?8. top marking? section and moved to page 18.
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